View 854S54AYI-08LF_3752174.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet ics854s54ayi-08 february 4, 2010 1 ?2010 integrated device technology, inc. octal 2:1 and 1:2 differential-to-lvds multiplexer ics854s54i-08 qa0 nqa0 gnd nqa1 v dd qb nqb qa1 qe0 qf nqf v dd nqe1 qe1 gnd nqe0 gnd qc1 nqc1 nqc0 v dd qc0 qd nqd qg0 nqh qh v dd nqg1 qg1 gnd nqg0 ninf inh ing1 inf nine1 ine1 nine0 ine0 v dd adr1 adr0 ninh gnd ing0 ning0 ning1 inb nina1 ina1 nina0 ina0 v dd sda sclk nind gnd inc0 ninc0 inc1 ind ninc1 ninb 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 general description the ics854s54i-08 is an octal 2:1 and 1:2 multiplexer. the device contains four individually controlled banks of lvds outputs. the 2:1 multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 mux switches one input to one of two outputs. this device is useful fo r multiplexing multi-rate ethernet phys which have 100m bit and 1000m bit transmit/receive pairs onto an optical sfp module which has a single transmit/receive pair. see application section for further information. the ics854s54i-08 is optimized for atca backplane swtich applications requiring very high performance and has a maximum operating frequency of 1.3ghz. the de vice is packaged in a small, 10mm x 10mm tqfp package, making it ideal for use on space-constrained boards. features ? four banks of three lvds output pairs ? twelve differential data intputs ? serial 1 2 c interface ? data pairs can accept the following differential input levels: lvpecl, lvds, cml ? maximum output frequency: 1.3ghz ? propagation delay: 1ns (maximum) ? additive phase jitter, rms: 0.066ps (typical) ? part-to-part skew: 475ps (maximum) ? full 3.3v supply voltage ? available in both standard (r0hs 5) and lead-free (rohs 6) packages ? -40c to 85c ambient operating temperature hiperclocks? ic s pin assignment ics854s54i-08 64-lead tqfp, e-pad 10mm x 10mm x 1.0mm package body y package to p v i ew
ics854s54ayi-08 february 4, 2010 2 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer block diagram 1 0 0 1 i 2 c 0 1 2 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 sel_qb mode_qax sel_qd mode_qcx sel_qf mode_qex sel_qh mode_qgx ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inc0 ninc0 qc0 nqc0 inc1 ninc1 qc1 nqc1 ing0 ning0 qg0 nqg0 ing1 ning1 qg1 nqg1 ine0 nine0 qe0 nqe0 ine1 nine1 qe1 nqe1 sda inb ninb qb nqb scl adr[1:0] ind nind qd nqd inf ninf qf nqf inh ninh qh nqh
ics854s54ayi-08 february 4, 2010 3 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 2 4, 5 qa0, nqa0 qa1, nqa1 output differential output pair. lvds interface levels. 3, 14, 26, 35, 46, 55 gnd power power supply ground. 6, 11, 23, 38, 43, 58 v dd power power supply pins. 7, 8 qb, nqb output differential output pair. lvds interface levels. 9, 10 nqf, qf output differential output pair. lvds interface levels. 12, 13 15, 16 nqe1, qe1 nqe0, qe0 output differential output pair. lvds interface levels. 17 ninf input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 18 inf input pulldown non-inverting differenti al lvpecl clock input. 19, 21 nine1, nine0 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 20, 22 ine1, ine0 input pulldown non-inverting differenti al lvpecl clock input. 24, 25 adr1, adr0 input pulldown serial address select pins. lvcmos / lvttl interface levels. 27, 29 ing0, ing1 input pulldown non-inverting differenti al lvpecl clock input. 28, 30 ning0, ning1 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 31 inh input pulldown non-inverting differenti al lvpecl clock input. 32 ninh input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 33, 34 36, 37 qg0, nqg0 qg1, nqg1 output differential output pair. lvds interface levels. 39, 40 qh, nqh output differential output pair. lvds interface levels. 41, 42 nqd, qd output differential output pair. lvds interface levels. 44, 45 47, 48 nqc1, qc1 nqc0, qc0 output differential output pair. lvds interface levels. 49 nind input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 50 ind input pulldown non-inverting differenti al lvpecl clock input. 51, 53 ninc1, ninc0 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 52, 54 inc1, inc0 input pulldown non-inverting differenti al lvpecl clock input. 56 sclk input pullup i 2 c serial address select pin. lvcmos/lvttl interface levels. 57 sda input pullup i 2 c shift register serial input. data sampled on the rising edge of sclk. lvcmos/lvttl interface levels. 59, 61 ina0, ina1 input pulldown non-inverting differenti al lvpecl clock input. 60, 62 nina0, nina1 input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 63 inb input pulldown non-inverting differenti al lvpecl clock input. 64 ninb input pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating.
ics854s54ayi-08 february 4, 2010 4 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer table 2. pin characteristics function tables table 3a. internal control input function table, sel_qb, mode_qax table 3b. internal control input function table, sel_qd, mode_qcx table 3c. internal control input function table, sel_qf, mode_qex table 3d. internal control input function table, sel_qh, mode_qgx symbol parameter test conditio ns minimum typical maximum units r pulldown input pulldown resistor 50 k ? r pullup input pullup resistor 50 k ? r vdd/2 pullup/pulldown resistors 50 k ? i 2 c bits outputs sel_qb mode_qax qb, nqb qa0, nqa0 qa1, nqa1 0 1 follows ina0, nina0 input follows inb, ninb input follows inb, ninb input 1 1 follows ina1, nina1 input follows inb, ninb input follows inb, ninb input x 0 high-impedance follows ina1, nina1 input follows ina0, nina0 input i 2 c bits outputs sel_qd mode_qcx qb, nqb qa0, nqa0 qa1, nqa1 0 1 follows inc0, ninc0 input follows ind, nind input follows ind, nind input 1 1 follows inc1, ninc1 input follows ind, nind input follows ind, nind input x 0 high-impedance follows inc1, ninc1 input follows inc0, ninc0 input i 2 c bits outputs sel_qf mode_qex qb, nqb qa0, nqa0 qa1, nqa1 0 1 follows ine0, nine0 input follows inf, ninf input follows inf, ninf input 1 1 follows ine1, nine1 input follows inf, ninf input follows inf, ninf input x 0 high-impedance follows ine1, nine1 input follows ine0, nine0 input i 2 c bits outputs sel_qh mode_qgx qb, nqb qa0, nqa0 qa1, nqa1 0 1 follows ing0, ning0 input follows i nh, ninh input follows inh, ninh input 1 1 follows ing1, ning1 input follows i nh, ninh input follows inh, ninh input x 0 high-impedance follows ing1, ning1 input follows ing0, ning0 input
ics854s54ayi-08 february 4, 2010 5 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer i 2 c control description the ics854s54i-08 uses an industry standard i 2 c interface to control the direction of the 4 separate 2:1, 1:2 mux switch blocks. each individual block is controlled by two bits of the 8 bit data byte. the data byte bit pairs are summarized as follows: control signals bit pair 1 ? ina0/nina0, ina1/n ina1, inb/ninb, qb/nqb sel_qb:mode_qax bit pair 2 ? inc0/ninc0, inc1/ninc1, ind/nind, qd/nqd sel_qd:mode_qcx bit pair 3 ? ine0/nine0, ine1/n ine1, inf/ninf, qf/nqf sel_qf:mode_qex bit pair 4 ? ing0/ning0, ing1/n ing1, inh/ninh, qh/nqh sel_qh:mode_qgx data byte 0 i 2 c addressing the ics854s54i-08 can be set to decode one of four addresses to minimize the chance of address conflict on the i 2 c bus. the address that is decoded is controlled by the setting of the adr_1, adr_0 (pins 24 and 25). bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 control bit mode_qgx sel_qh mode_qex sel_qf m ode_qcx sel_qd mode_qax sel_qb power-up default value 10101010 adr_sel (pins 24 & 25) = default (1, 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1101111r/w adr_sel (pins 24 & 25) = default (1, 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1101110r/w adr_sel (pins 24 & 25) = default (0, 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1101101r/w adr_sel (pins 24 & 25) = default (0, 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1101100r/w
ics854s54ayi-08 february 4, 2010 6 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer s ecure i 2 c i nterface - p rotocol the ics854s54i-08 is a slave-only device and uses the standard i 2 c protocol as shown in the below diagrams. the maximum sclk frequency is greater than 400khz whic h is more than sufficient for standard i 2 c clock speeds. start (st) ? defined as high-to-low transition on sda while holding sclk high. data ? between start and stop cycles, sda is synchronous with sclk. data may change only when sclk is low and must be stable when sclk is high. acknowledge (ak) ? sda is driven low before the sclk rising edge and held low until the sclk falling edge. stop (sp) ? defined as low-to-high transition on sda while holding sclk high. serial interface ? a write example a serial transfer to the ics854s54i-08 always consists of an address cycle followed by a single data byte. any additional data bytes will not be acknowledged and the ics854s54i-08 will leave the data bus high. these extra bits will not be loaded into the serial control register. once the data byte is loaded and the master generates a stop condition, the values in the serial control register are latched into the mux control bit outputs and each mux will switch into the new state. sclk sda start valid data acknowledge stop st slave address: 7 bits r/w ak 1 bit refer to page 5 for address choices based on addr_sel pin setting 1 bit 1 bit data byte 0: 8 bits ak sp mode_qgx sel_qh mode_qex sel_qf mode_qc x sel_qd mode_qax sel_qb 1 bit 1 bit
ics854s54ayi-08 february 4, 2010 7 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl input dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma operating temperature range, t a -40c to +85c package thermal impedance, ja 25.6c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 392 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current sda, sclk v dd = v in = 3.465v 10 a adr0, adr1 v dd = v in = 3.465v 150 a i il input low current sda, sclk v dd = 3.465v, v in = 0v -150 a adr0, adr1 v dd = 3.465v, v in = 0v -10 a
ics854s54ayi-08 february 4, 2010 8 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: v il cannot be less than -0.3v. note 2: common mode voltage is define as v ih. table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 5. ac electrical characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when th e device is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input cro ssing point to the different ial output crossing point. note 2: defined as skew between outputs on different devices operating at the same supply voltage, same frequency and with equa l load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: measured using standard lvds input at 622mhz. symbol parameter test conditio ns minimum typical maximum units i ih input high current ina[0:1], inb, inc[0:1], ind, ine[0:1], inf, ing[0:1], inh v dd = v in = 3.465v 150 a nina[0:1], ninb, inc[0:1], nind, nine[0:1], ninf, ning[0:1], ninh v dd = v in = 3.465v 150 a i il input low current ina[0:1], inb, inc[0:1], ind, ine[0:1], inf, ing[0:1], inh v dd = 3.465v, v in = 0v -10 a nina[0:1], ninb, inc[0:1], nind, nine[0:1], ninf, ning[0:1], ninh v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak input voltage; note 1 0.15 1.3 v v cmr common mode input voltage: note 1, 2 1.2 v dd v symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 325 425 525 mv ? v od v od magnitude change 50 mv v os offset voltage 1.25 1.35 1.50 v ? v os v os magnitude change 50 mv symbol parameter test conditions minimum typical maximum units f max output frequency 1.3 ghz t pd propagation delay; note 1 all outputs 0.525 1.0 ns t jit buffer additive ph ase jitter, rms; refer to additive phase jitter section 622.08mhz, integration range: 12khz ? 20mhz 0.066 ps t sk(pp) part-to-part skew; note 2, 3 475 ps mux_ is olation mux isolation; note 4 45 db t r / t f output rise/ fall time 20% to 80% 50 385 ps
ics854s54ayi-08 february 4, 2010 9 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer additive phase jitter the spectral purity in a band at a s pecific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expr essed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the des ired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificati ons, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator "ifr2042 10k hz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". additive phase jitter @ 622.08mhz 12khz to 20mhz = 0.066ps (typical) ssb phase noise dbc/hz offset from carr ier frequency (hz)
ics854s54ayi-08 february 4, 2010 10 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer parameter measurement information output load ac test circuit propagation delay mux isolation differential input levels part-to-part skew output rise/fall time scope qx nqx lvds 3.3v5% power supply +? float gnd v dd t pd nqxx qxx ninxx inxx where x = a, b, c, d, e, f, g, h amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1 ninxx inxx v dd gnd v cmr cross points v pp where x = a, b, c, d, e, f, g, h t sk(pp) part 1 part 2 qx qy nqx nqy nqxx qxx nqxx qxx t sk(b)
ics854s54ayi-08 february 4, 2010 11 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer parameter measurement information, continued offset voltage setup differential output voltage setup out out lvds dc input ? ? ? v os / ? v os v dd ? ? ? 100 out out lvds dc input v od / ? v od v dd
ics854s54ayi-08 february 4, 2010 12 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer application information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. in/nin inputs for applications not requiring the use of a differential input, both the in and nin pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from in to ground. outputs: lv d s o u t p u t s all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. wiring the differential input to accept single-ended levels figure 1 shows how the differential input can be wired to accept single-ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. fo r example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ended signal driving differential input single ended clock input v dd inx ninx r1 c1 0.1u r2 1k 1k v_ref
ics854s54ayi-08 february 4, 2010 13 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer lvpecl differential clock input interface the in /nin accepts lvpecl, cml, lvds and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 2a to 2d show interface examples for the in /ni n input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. in/nin input driven by an open collector cml driver figure 2c. hiperclocks in/nin input driven by a 3.3v lvpecl driver figure 2b. in/nin input driven by a built-in pullup cml driver figure 2d. in/nin input driven by a 3.3v lvds driver in nin lvpecl differential inputs cml 3.3v zo = 50 ? zo = 50 ? 3.3v 3.3v r1 50 r2 50 3.3v r1 100 lvpecl in nin 3.3v zo = 50 ? zo = 50 ? lvpecl differential inputs 3.3v r1 100 cml built-in pullup in nin 3.3v zo = 50 ? zo = 50 ? lvpecl differential inputs 3.3v r1 100 lvds in nin 3.3v zo = 50 ? zo = 50 ? lvpecl differential inputs
ics854s54ayi-08 february 4, 2010 14 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the ou ter edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb pr ovides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the groun d plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ? heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is in corporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 3. assembly for exposed pad thermal release path - side view (drawing not to scale) 3.3v lvds driver termination a general lvds interface is shown in figure 4. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 4. typical lvds driver termination ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder 3.3v lvds driver r1 100 ? + 3.3v 50 50 100 differential transmission line
ics854s54ayi-08 february 4, 2010 15 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer a typical application using one bank of the ics854s54i-08 used to connect advanced mezzanine cards to atca backplane. also provdes ability to cross connect individual amc?s to each other. problem addressed: how to allow communication between amc cards while backplane channels are disabled. mode 1 (sel_qb = 0, mode _qax = 1), amc_1 to at ca backplane communication atca tx (inb, ninb) connected to (qa0/nqa0, qa1/nqa1) amc_1_rx and amc_2_rx respectively. atca_rx (qb, nqb) connected to amc_1, tx (ina0, nina0). 1 0 0 1 0 1 ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inb ninb qb nqb atca hub board to backplane sel_qb mode_qax amc_1 amc_2 1 0 0 1 0 1 ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inb ninb qb nqb atca_tx atca_rx amc_1_tx amc_1_rx amc_2_tx amc_2_rx atca backplane sel_qb mode_qax atca communication path b q _ l e sx a q _ e d o md e t c e l e s e d o m 0 1 d e t c e l e s 1 c m a 11 d e t c e l e s 2 c m a x0 , d e t c e n n o c 2 c m a & 1 c m a z - i h = b q n / b q
ics854s54ayi-08 february 4, 2010 16 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer mode 2 (sel_qb = 1, mode _qax = 1), amc_2 to at ca backplane communication tca tx (inb, ninb) connected to (qa0/nqa0, qa1/nqa1) amc_1_rx and amc_2_rx respectively. atca_rx (qb, nqb) connected to amc_2, tx (ina1, nina1). mode 3 (sel_qb = x, mode_qax = 0) , amc_1 to amc_2 communication atca_rx disabled: (qb and nqb = hi-z) amc_1 tx (i na0, nina0) connected to amc_2 rx (qa1, nqa1), amc_2 tx (ina1, nina1) connected to amc_1 rx (qa0, nqa0). 1 0 0 1 0 1 ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inb ninb qb nqb atca_tx atca_rx amc_1_tx amc_1_rx amc_2_tx amc_2_rx atca backplane sel_qb mode_qax 1 0 0 1 0 1 ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inb ninb qb nqb atca_tx atca_rx amc_1_tx amc_1_rx amc_2_tx amc_2_rx atca backplane sel_qb mode_qax atca communication path atca communication path b q _ l e sx a q _ e d o md e t c e l e s e d o m 01 d e t c e l e s 1 c m a 11 d e t c e l e s 2 c m a x 0 , d e t c e n n o c 2 c m a & 1 c m a z - i h = b q n / b q b q _ l e sx a q _ e d o md e t c e l e s e d o m 01 d e t c e l e s 1 c m a 1 1 d e t c e l e s 2 c m a x0 , d e t c e n n o c 2 c m a & 1 c m a z - i h = b q n / b q
ics854s54ayi-08 february 4, 2010 17 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer power considerations this section provides information on power dissipati on and junction temperature for the ics854s54i-08. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics854s54i-08 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v dd_max * i dd_max = 3.465v * 365ma = 1264.725mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 25.6c/w per table 6 below. therefore, tj for an ambient temperatur e of 85c with all outputs switching is: 85c + 1.265w * 25.6c/w = 117.4c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary de pending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 64 lead tqfp, e-pad forced convection ja by velocity meters per second 0 multi-layer pcb, jedec st andard test boards 25.6c/w
ics854s54ayi-08 february 4, 2010 18 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer reliability information table 7. ja vs. air flow table for a 64 lead tqfp, e-pad transistor count the transistor count for ics854s54i-08 is: 6233 ja vs. air flow meters per second 0 multi-layer pcb, jedec standard test boards 25.6c/w
ics854s54ayi-08 february 4, 2010 19 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer package outline and package dimensions package outline - y suffix for 64 lead tqfp, e-pad table 8. package dimensions for 64 lead tqfp, e-pad reference document: jedec publication 95, ms-026 jedec variation: acd all dimensions in millimeters symbol minimum nominal maximum n 64 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d & e 12.00 basic d1 & e1 10.00 basic d2 & e2 7.50 ref. d3 & e3 4.5 5.5 e 0.50 basic l 0.45 0.60 0.75 0 7 ccc 0.08 -hd version exposed pad down
ics854s54ayi-08 february 4, 2010 20 ?2010 integrated device technology, inc. ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 854s54ayi-08 ics854s54ayi08 lead-free, 64 lead tqfp, e-pad tray -40 c to 85 c 854s54ayi-08t ics854s54ayi08 lead-free, 64 lead tqfp, e-pad 500 tape & reel -40 c to 85 c 854S54AYI-08LF ics854s54ai08l lead-free, 64 lead tqfp, e-pad tray -40 c to 85 c 854S54AYI-08LF ics854s54ai08l lead-free, 64 lead tqfp, e-pad 500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change an y circuitry or specifications wit hout notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics854s54i-08 data sheet octal 2:1 and 1:2 differential-to-lvds multiplexer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

▲Up To Search▲

Price & Availability of 854S54AYI-08LF

	To Download 854S54AYI-08LF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .